Limits on Silicon Nanoelectronics for Terascale Integration
James D. Meindl,*
Qiang Chen,
Jeffrey A. Davis
Throughout the past four decades, silicon semiconductor
technology has advanced at exponential rates in both performance and productivity. Concerns have been raised, however, that the limits of
silicon technology may soon be reached. Analysis of fundamental, material, device, circuit, and system limits reveals that silicon technology has an enormous remaining potential to achieve terascale integration (TSI) of more than 1 trillion transistors per chip. Such massive-scale integration is feasible assuming the development and
economical mass production of double-gate metal-oxide-semiconductor field effect transistors with gate oxide thickness of about 1 nanometer, silicon channel thickness of about 3 nanometers, and channel
length of about 10 nanometers. The development of interconnecting wires
for these transistors presents a major challenge to the achievement of
nanoelectronics for TSI.
School of Electrical and Computer Engineering, Microelectronics
Research Center, Georgia Institute of Technology, Atlanta, GA
30332-0269, USA.
*
To whom correspondence should be addressed. E-mail:
james.meindl{at}mirc.gatech.edu
