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Science 12 June 1998:
Vol. 280. no. 5370, pp. 1716 - 1721
DOI: 10.1126/science.280.5370.1716
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Review

A Defect-Tolerant Computer Architecture: Opportunities for Nanotechnology

James R. Heath, Philip J. Kuekes, Gregory S. Snider, R. Stanley Williams

Teramac is a massively parallel experimental computer built at Hewlett-Packard Laboratories to investigate a wide range of different computational architectures. This machine contains about 220,000 hardware defects, any one of which could prove fatal to a conventional computer, and yet it operated 100 times faster than a high-end single-processor workstation for some of its configurations. The defect-tolerant architecture of Teramac, which incorporates a high communication bandwidth that enables it to easily route around defects, has significant implications for any future nanometer-scale computational paradigm. It may be feasible to chemically synthesize individual electronic components with less than a 100 percent yield, assemble them into systems with appreciable uncertainty in their connectivity, and still create a powerful and reliable data communications network. Future nanoscale computers may consist of extremely large-configuration memories that are programmed for specific tasks by a tutor that locates and tags the defects in the system.

J. R. Heath is in the Department of Chemistry and Biochemistry, University of California at Los Angeles, Los Angeles, CA 90095-1569, USA. P. J. Kuekes, G. S. Snider, and R. S. Williams are at Hewlett-Packard Laboratories, Palo Alto, CA 94304-1392, USA.

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